A typical test waveform generator is depicted in FIG. 1. With such a waveform generator, a desired test waveform T.sub.OUT is generated on the basis of timing pulses TG1, TG2 from timing generators 12a, 12b as well as vector information VD from a vector generator, e.g., a vector memory 10. The vector information VD is a pattern comprised of a sequence of "1"and/or "0"s, but it does not include information concerning the timing of the test waveform, i.e., the time intervals between the respective pulse waveforms that make up the test waveform. The test waveform T.sub.OUT of a desired format is generated by combining the vector information VD and timing pulses TG1, TG2 by a formatter, e.g., a flip-flop circuit 13 in combination with an AND gate 14.
Referring now to FIGS. 1 and 2, timing data memories 11a, 11b output timing information (e.g., the contents of one memory includes delay times t.sub.1, t.sub.2 which are described below) to the timing generators 12a, 12b. The timing pulses TG1, TG2 are output by the timing generators 12a, 12b to a set terminal S and a reset terminal R of a flip-flop (FF) circuit 13 upon the lapse of delay times t.sub.1, t.sub.2 following the rising edge of a period clock signal CLK. Meanwhile, the vector memory 10 (corresponding to a vector generator) outputs for each period of the period clock signal CLK the vector information VD ("1" or "0") stored at an address designated by an address counter 15. The AND gate 14 then combines the vector information VD and the output of the FF circuit 13 and outputs the test waveform T.sub.OUT.
It should be noted that in FIG. 2 the test waveform T.sub.OUT is of the RZ (return-to-zero) type in period I and IV and the NRZ (non-return-to-zero) type in period III, i.e., T.sub.OUT is in mixed form.
It should also be noted that, in a frequently-adopted alternative arrangement (not shown), timing generators are used instead of the timing data memories 11a, 11b, fixed timing pulses TG1, TG2 are constantly output from the timing generators 12a, 12b, and a waveform is generated by only varying the "1" and "0"signals of the vector memory 10.
A disadvantage of the above-described test waveform generators is that, in a case where it is necessary to change the kind of test waveform and the timing of the test waveform (e.g., in a case where an on-the-fly function is required), there is an inconvenience in that settings of the timing generators 12a, 12b and vector memory 10 must be changed. That is, in the above-described case it is also necessary to change both the timing information stored in the timing data memories 11a, 11b for each period and the "1"and "0"outputs of the vector memory 10.
In addition, the data encoded on the test waveform is in many cases prepared on the basis of simulation data for a CAE system. That simulation data includes timing information concerning times at which the vector is inverted. In a case where a vector is generated from such vector data by using a conventional formatter, it is necessary to divide the vector data into predetermined time intervals (periods) and define the vector data in terms of elements of timing (e.g., time delays t.sub.1, t.sub.2, shown in FIG. 2) and elements of the vector magnitude ("1", 37 0"). In this case, however, there is a drawback in that the translation software is complicated.
Furthermore, in the case where the timing pulses TG1, TG2 are constantly generated by the timing generators 12a, 12b and the waveform is generated by only varying the signals "1", "0" of the vector memory 10, there is a drawback in that if the vector memory 10 continuously outputs "8" as the vector information, the timing generators 12a, 12b constantly output the timing pulses TG1, TG2.